71 lines
1.7 KiB
Systemverilog
71 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Gate deduplication through function argument
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Jose Tejada
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// SPDX-License-Identifier: CC0-1.0
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module jtcop_bac06 (
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input rst,
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input clk,
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input [15:0] cpu_dout,
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input [12:1] cpu_addr,
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input [1:0] cpu_dsn,
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input [7:0] st_addr,
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output reg [7:0] st_dout
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);
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reg [7:0] mode[0:3];
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reg [15:0] hscr, vscr;
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reg [3:0] colscr_sh, rowscr_sh;
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reg [7:0] def_cfg[0:15];
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always @(posedge clk) begin
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case (st_addr[3:0])
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0, 1, 2, 3: st_dout <= mode[st_addr[1:0]];
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4: st_dout <= hscr[7:0];
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5: st_dout <= hscr[15:8];
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6: st_dout <= vscr[7:0];
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7: st_dout <= vscr[15:8];
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8: st_dout <= {colscr_sh, rowscr_sh};
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default: st_dout <= '0;
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endcase
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end
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function [15:0] combine(input [15:0] din);
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combine = {cpu_dsn[1] ? din[15:8] : cpu_dout[15:8], cpu_dsn[0] ? din[7:0] : cpu_dout[7:0]};
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endfunction
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always @(posedge clk) begin
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if (rst) vscr <= {def_cfg[7], def_cfg[6]};
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else
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case (cpu_addr[2:1])
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0: hscr <= combine(hscr);
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1: vscr <= combine(vscr);
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2: colscr_sh <= cpu_dout[3:0];
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3: rowscr_sh <= cpu_dout[3:0];
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endcase
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end
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endmodule
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module jtcop_game (
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input clk,
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output [7:0] st_dout
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);
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wire [12:1] cpu_addr;
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jtcop_main u_main (.cpu_addr(cpu_addr));
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jtcop_bac06 u_ba2 (
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.rst(rst),
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.clk(clk),
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.cpu_dout(ba2_din),
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.cpu_addr(cpu_addr),
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.cpu_dsn(ba2_dsn),
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.st_addr(st_addr),
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.st_dout(st_dout)
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);
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endmodule
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module jtcop_main (
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output [12:1] cpu_addr
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);
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assign cpu_addr = '0;
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endmodule
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