33 lines
645 B
Systemverilog
33 lines
645 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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always @(negedge clk) begin // negedge so there is nothing after $finish
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cyc <= cyc + 1;
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if (cyc == 12) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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clocking cb @(posedge clk);
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endclocking
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default clocking cb;
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initial begin
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##2;
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if ($time != 20) $stop;
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##5;
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if ($time != 70) $stop;
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##3;
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if ($time != 100) $stop;
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end
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endmodule
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