23 lines
589 B
Systemverilog
23 lines
589 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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// verilog_lint: off
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// verilog_format: on
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module t (input clk);
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logic a, b, c, d;
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// LHS length 2, RHS length 4 -- WIDTHTRUNC (left < right)
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assert property (@(posedge clk)
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(a ##1 b) intersect (c ##3 d));
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// LHS length 4, RHS length 2 -- WIDTHEXPAND (left > right)
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assert property (@(posedge clk)
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(a ##3 b) intersect (c ##1 d));
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endmodule
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