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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t #(parameter P);
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generate
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var j;
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for (j=0; P; j++)
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initial begin end
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endgenerate
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endmodule
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