95 lines
1.9 KiB
Systemverilog
95 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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function automatic int align(input int a, input int b);
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return a - (a % b);
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endfunction
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class Foo;
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static function int mul(input int a, input int b);
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return a * b;
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endfunction
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endclass
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class FooParam #(
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parameter int param = 5
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);
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static function int mul(input int a);
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return a * param;
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endfunction
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endclass
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class Base #(
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parameter int param = 5
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);
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function int get_base_param();
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return param;
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endfunction
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static function int alignUp(input int a);
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return ((a + param - 1) / param) * param;
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endfunction
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endclass
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class Derived #(
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parameter int a = 17,
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parameter int b = 8,
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parameter int c = align(a, b),
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parameter int d = Base#(b)::alignUp(a),
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parameter int e = Foo::mul(a, b),
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parameter int f = FooParam#()::mul(a)
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) extends Base #(
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.param(a)
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);
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function int get_third_param();
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return c;
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endfunction
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function int get_fourth_param();
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return d;
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endfunction
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function int get_fifth_param();
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return e;
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endfunction
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function int get_sixth_param();
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return f;
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endfunction
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endclass
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module t (
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clk
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);
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input clk;
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Derived inst = new;
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always @(posedge clk) begin
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`checkh(inst.get_base_param(), 17)
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`checkh(inst.get_third_param(), 16)
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`checkh(inst.get_fourth_param(), 24)
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`checkh(inst.get_fifth_param(), 136)
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`checkh(inst.get_sixth_param(), 85)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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