75 lines
2.2 KiB
Systemverilog
75 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input logic clk
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);
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localparam OP_UNTYPED = 3'b000;
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localparam logic [2:0] OP_LOGIC = 3'b011;
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localparam logic [2:0] OP_WILD = 3'b1x1;
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logic [4:0] cyc = 0;
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logic [2:0] opcode;
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int hit_untyped = 0;
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int hit_logic = 0;
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int hit_wild = 0;
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int hit_sampled = 0;
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int hit_past = 0;
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int hit_past_n = 0;
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int hit_stable = 0;
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int hit_norose = 0;
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int hit_nofell = 0;
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int hit_nochanged = 0;
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int hit_wild_samp = 0;
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always @(posedge clk) if (cyc != 5'd31) cyc <= cyc + 1;
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assign opcode = (cyc < 16) ? cyc[2:0] : 3'b010;
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assert property (@(posedge clk) opcode inside {OP_UNTYPED}) hit_untyped++;
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assert property (@(posedge clk) opcode inside {OP_LOGIC}) hit_logic++;
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assert property (@(posedge clk) opcode ==? OP_WILD) hit_wild++;
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assert property (@(posedge clk) $sampled(OP_LOGIC) == OP_LOGIC) hit_sampled++;
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assert property (@(posedge clk) $past(OP_LOGIC) == OP_LOGIC) hit_past++;
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assert property (@(posedge clk) $past(OP_LOGIC, 3) == OP_LOGIC) hit_past_n++;
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assert property (@(posedge clk) $stable(OP_LOGIC)) hit_stable++;
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assert property (@(posedge clk) !$rose(OP_LOGIC)) hit_norose++;
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assert property (@(posedge clk) !$fell(OP_LOGIC)) hit_nofell++;
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assert property (@(posedge clk) !$changed(OP_LOGIC)) hit_nochanged++;
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assert property (@(posedge clk) $sampled(OP_WILD) === OP_WILD) hit_wild_samp++;
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always @(posedge clk) begin
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if (cyc == 24) begin
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`checkd(hit_untyped, 2);
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`checkd(hit_logic, 2);
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`checkd(hit_wild, 4);
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`checkd(hit_sampled, 24);
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`checkd(hit_wild_samp, 24);
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`checkd(hit_nofell, 24);
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`checkd(hit_past, 23);
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`checkd(hit_stable, 23);
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`checkd(hit_norose, 23);
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`checkd(hit_nochanged, 23);
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`checkd(hit_past_n, 21);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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