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https://github.com/verilator/verilator.git
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Geza Lore
9e03fed56b
Companion to #8476, and this now moves all instance array and interface array/modport array port expansion into elaboration. Fixes #2675. Arrays of interface instances and interface array ports are now split into their elements during elaboration, instead of after V3Width in V3Inst::dearrayAll, which is removed. Background: next to every interface instance 'intf ifs()', V3LinkCells creates a companion variable 'ifs__Viftop' of type IfaceRefDType referring to the instance, so the instantiating module can use the interface as a value (in pin connections, virtual interface assignments, arguments, ...) just like a module referring to it through an interface port. For an array of instances 'intf ifs[N]()', this variable is an unpacked array of IfaceRefDType, but an IfaceRefDType can only refer to a single instance, so it must be split into a variable for each element, and every use of the whole array replaced. V3Param expands interface instance arrays like module instance arrays, also splitting the __Viftop variable referencing the whole array into a variable for each element cell ('ifs__BRA__i__KET____Viftop', the companion of element cell 'ifs__BRA__i__KET__'), and splits each interface array port into a variable for each element. The whole array variables remain until all references to them are replaced, so V3LinkDot can link hierarchical references to the correct specialization. In V3Width, every reference to a whole interface array, including hierarchical ones, is replaced by an AstInitArray of references to its element variables, typed as the whole array, e.g. 'ifs' becomes '{ifs[0], ifs[1], ...}. The AstInitArray keeps its own type, so its uses are checked as those of the whole array. The whole array variables are removed at the end of V3Width. V3Width then treats a whole interface array replaced by an AstInitArray as an ordinary unpacked array value: - A constant select yields the element, a slice the selected elements. - A pin of an element of a module instance array selects its part of an interface array connection like any other connection. - A pin of an interface array port is split into a pin for each element port, connected left index to left index. - A member of an element is referenced through the interface, as for any other interface. This supports slices of interface arrays, and interface ports of multi-dimensional module instance arrays connected to interface arrays.
94 lines
2.2 KiB
Systemverilog
94 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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interface a_if;
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int x;
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endinterface
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typedef virtual a_if va_t;
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module sub;
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a_if ifs[2] ();
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for (genvar i = 0; i < 2; ++i) begin : g
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initial ifs[i].x = 'h40 + i;
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end
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endmodule
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class C;
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va_t vif[2];
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endclass
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module t;
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a_if asc[0:3] ();
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a_if desc[3:0] ();
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a_if a2d[1:0][0:2] ();
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for (genvar i = 0; i < 4; ++i) begin : g_1d
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initial begin
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asc[i].x = 'h10 + i;
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desc[i].x = 'h20 + i;
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end
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end
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for (genvar i = 0; i < 2; ++i) begin : g_2d_i
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for (genvar j = 0; j < 3; ++j) begin : g_2d_j
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initial a2d[i][j].x = 'h30 + 3 * i + j;
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end
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end
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va_t w[4];
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va_t s[2];
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va_t w2d[2][3];
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C c;
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sub i_sub ();
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initial begin
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#1;
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// Whole array, left element to left element
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w = asc;
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for (int i = 0; i < 4; ++i) `checkh(w[i].x, 'h10 + i);
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w = desc;
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for (int i = 0; i < 4; ++i) `checkh(w[i].x, 'h20 + 3 - i);
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// Slices
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s = asc[1:2];
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`checkh(s[0].x, 'h11);
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`checkh(s[1].x, 'h12);
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s = desc[2:1];
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`checkh(s[0].x, 'h22);
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`checkh(s[1].x, 'h21);
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// Multi dimensional, a2d[1] is the left row
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w2d = a2d;
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for (int i = 0; i < 2; ++i) begin
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for (int j = 0; j < 3; ++j) `checkh(w2d[i][j].x, 'h30 + 3 * (1 - i) + j);
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end
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// Hierarchical reference to a whole array
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s = i_sub.ifs;
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`checkh(s[0].x, 'h40);
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`checkh(s[1].x, 'h41);
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`checkh(i_sub.ifs[0].x, 'h40);
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`checkh(i_sub.ifs[1].x, 'h41);
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// Class member
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c = new;
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c.vif = asc[2:3];
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`checkh(c.vif[0].x, 'h12);
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`checkh(c.vif[1].x, 'h13);
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// Writes through the virtual interfaces reach the instances
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c.vif[1].x = 'h99;
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w2d[0][2].x = 'h98;
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#1;
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`checkh(asc[3].x, 'h99);
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`checkh(a2d[1][2].x, 'h98);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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