Wilson Snyder d396c55e34 In --xml-only show module_files and cells ala Verilog-Perl vhier, msg2716.

2018-11-01 19:53:26 -04:00

..

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In --xml-only show module_files and cells ala Verilog-Perl vhier, msg2716.

2018-11-01 19:53:26 -04:00

.gdbinit

Debug: Add default .gdbinit file

2012-03-02 20:59:47 -05:00

.gitignore

Tests: Support multiple scenario testing.

2018-05-07 20:42:28 -04:00

driver.pl

Tests: Add VERILATOR_MAKE override variable.

2018-10-30 20:28:39 -04:00

input.vc

Convert repository to git from svn.

2008-06-09 21:25:10 -04:00

Makefile

MAJOR: Add multithreaded model generation.

2018-07-22 20:54:28 -04:00

Makefile_obj

Tests: Fix misc multithreaded issues, merge from threads branch.

2018-05-19 09:30:54 -04:00

vgen.pl

Copyright year update. No functional change.

2018-01-02 18:05:06 -05:00