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49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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byte array1[];
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byte array2[];
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byte queue1[$];
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byte queue2[$];
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byte byte_e;
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initial begin
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queue2 = {8'ha, 8'hb};
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array2 = {8'hc, 8'hd};
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byte_e = 8'he;
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array1 = {byte_e};
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`checkd(array1[0], 8'he);
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array1 = {queue2};
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`checkd(array1[0], 8'ha);
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`checkd(array1[1], 8'hb);
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array1 = {array2};
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`checkd(array1[0], 8'hc);
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`checkd(array1[1], 8'hd);
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queue1 = {byte_e};
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`checkd(queue1[0], 8'he);
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queue1 = {queue2};
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`checkd(queue1[0], 8'ha);
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`checkd(queue1[1], 8'hb);
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queue1 = {array2};
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`checkd(queue1[0], 8'hc);
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`checkd(queue1[1], 8'hd);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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