Ryszard Rozak 7d2b6bd921 Internals: Optimize updates of Vtogcov signals. No functional change intended. (#6110)		2025-08-04 13:29:56 +01:00
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t	Internals: Optimize updates of Vtogcov signals. No functional change intended. (#6110)	2025-08-04 13:29:56 +01:00
.gdbinit	…
.gitignore	…
CMakeLists.txt	…
Makefile	…
Makefile_obj	Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk.	2025-07-28 18:01:50 -04:00
driver.py	Tests: Switch to measuring CPU time instead of real time in test timeouts (#6224)	2025-07-24 11:27:02 +02:00
input.vc	…
input.xsim.vc	…