58 lines
1.2 KiB
Systemverilog
58 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task test_read(input integer f, output string l);
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automatic string line;
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automatic string buffer = "";
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automatic integer code;
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if (f == 0) $stop;
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while (1) begin
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code = $fgets(line, f);
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// Uncomment for issue #7976 workaround
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// $display("code %d => content: %s", code, line);
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buffer = {buffer, line};
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if (line == "") begin
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break;
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end
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end
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l = buffer;
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endtask
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task test_eof_tsk;
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automatic integer fd;
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automatic string test_file_name = "t/t_sys_fgets_loop.dat";
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automatic string output_line;
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// Open files
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fd = $fopen(test_file_name, "r");
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if (fd == 0) begin
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$display("ERROR ould not open file '%s' for reading aborting", test_file_name);
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$fatal(0);
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end
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while (!$feof(
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fd
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)) begin
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test_read(fd, output_line);
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end
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$fclose(fd);
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endtask
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initial begin
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test_eof_tsk;
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end
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initial begin
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#100;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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