284 lines
7.0 KiB
Systemverilog
284 lines
7.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off BLKSEQ
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// verilator lint_off DECLFILENAME
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module t(/*AUTOARG*/
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// Inputs
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clk, reset_l
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);
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input clk;
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input reset_l;
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parametrized_initial#(.REPETITIONS(0)) parametrized_initial0();
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parametrized_initial#(.REPETITIONS(1)) parametrized_initial1();
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parametrized_initial#(.REPETITIONS(2)) parametrized_initial2();
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non_parametrized_initial non_parametrized_initial();
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with_always with_always(.clk(clk));
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const_condition const_condition();
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loop_with_param loop_with_param();
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if_with_param if_with_param();
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clock_init_race clock_init_race(.clk(clk), .reset_l(reset_l));
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endmodule
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// module unused - no warning for any of statements inside
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module unused(input clk);
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bit unused_variable_while;
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bit unused_variable_do_while;
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bit unused_variable_for;
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const bit always_false = 0;
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always @(posedge clk) begin
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while(unused_variable_while) begin
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unused_variable_while <= 1;
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end
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do begin
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unused_variable_do_while <= 1;
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end while (unused_variable_do_while);
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for (int i = 0; i < 5; i++)
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begin
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unused_variable_for <= 1;
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end
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while(always_false) begin
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$write("This will not be printed\n");
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end
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do begin
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$write("This will not be printed\n");
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end while (always_false);
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for (int i = 0; always_false; i++)
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begin
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$write("This will not be printed\n");
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end
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end
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endmodule
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// no warning for loops under parameterized module
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module parametrized_initial #(parameter REPETITIONS = 0);
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int prints_while = 0;
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int prints_do_while = 0;
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// loops with evaluation depending on REPETITIONS
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initial begin
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while(prints_while < REPETITIONS) begin
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prints_while = prints_while + 1;
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$write("Writing to console to avoid loop being optimized out\n");
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end
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while(REPETITIONS < 0) begin
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$write("Writing to console to avoid loop being optimized out\n");
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end
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for (int i = 0; i < REPETITIONS; i++) begin
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$write("Writing to console to avoid loop being optimized out\n");
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end
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do begin
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prints_do_while = prints_do_while + 1;
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$write("Writing to console to avoid loop being optimized out\n");
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end while (prints_do_while < REPETITIONS);
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end
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// loop not changing variable used for output
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int param_unused_while = 0;
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initial begin
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while(param_unused_while < REPETITIONS) begin
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param_unused_while = param_unused_while + 1;
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end
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end
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const logic always_false = 0;
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// loops with empty bodies
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initial begin
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while(0);
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while(always_false);
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while(REPETITIONS < 0);
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end
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endmodule
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module non_parametrized_initial;
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int prints_do_while = 0;
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const int always_zero = 0;
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// loops with evaluation depending on always_zero
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initial begin
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while(always_zero < 0) begin
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$write("This will not be printed\n");
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end
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// unrolled - no warning
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for (int i = 0; i < always_zero; i++) begin
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$write("This will not be printed\n");
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end
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// inlined - no warning
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do begin
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prints_do_while = prints_do_while + 1;
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$write("Writing to console to avoid loop being optimized out\n");
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end while (prints_do_while < always_zero);
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end
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// loop not changing variable used for output
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int param_unused_while = 0;
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int param_unused_do_while = 0;
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int param_unused_for = 0;
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initial begin
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// warning
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while(param_unused_while < always_zero) begin
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param_unused_while++;
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end
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// unrolled - no warning
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for (int i = 0; i < 5; i++)
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begin
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param_unused_for = 1;
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end
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// inlined - no warning
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do begin
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param_unused_do_while = 1;
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end while (param_unused_do_while > 0);
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end
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const logic always_false = 0;
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// loops with empty bodies - warning
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initial begin
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while(0);
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while(always_false);
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while(always_zero < 0);
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do ; while(0);
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// unrolled - no warning
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for (int i = 0; i < 1; i++);
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end
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endmodule
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// warning for all unused loops under always
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module with_always(input clk);
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const logic always_false = 0;
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always @(posedge clk) begin
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while(0);
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while(always_false) begin
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$write("Test");
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end
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end
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endmodule
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module const_condition;
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const logic always_zero = 0;
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// loops with const false condition - warning
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initial begin
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while(always_zero) begin
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$write("This will not be printed\n");
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end
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for (int i = 0; always_zero; i++)
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begin
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$write("This will not be printed\n");
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end
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for (int i = 0; i < always_zero; i++)
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begin
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$write("This will not be printed\n");
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end
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// inlined - no warning
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do begin
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$write("This will be printed\n");
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end while (always_zero);
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end
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endmodule
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// loop with param - no warning
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module loop_with_param;
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parameter ZERO_PARAM = 0;
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int prints = 2;
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initial begin
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for (int i = 0; ZERO_PARAM; i++) begin
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$write("This will not be printed\n");
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end
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while (ZERO_PARAM != ZERO_PARAM) begin
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$write("This will not be printed\n");
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end
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while(prints > ZERO_PARAM) begin
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prints--;
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end
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end
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endmodule
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module if_with_param;
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parameter ZERO_PARAM = 0;
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parameter ONE_PARAM = 1;
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initial begin
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if (ZERO_PARAM) begin
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// loop under false parameterized if - no warning
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int prints = 0;
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while(prints < 5) begin
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prints++;
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end
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$write("Prints %d\n", prints);
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end else if (!ONE_PARAM) begin
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// loop under false parameterized if - no warning
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int prints = 0;
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while(prints < 5) begin
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prints++;
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end
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$write("Prints %d\n", prints);
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end else begin
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// loop under true parameterized if - no warning
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int prints = 0;
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while(prints < 5) begin
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prints++;
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end
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$write("Prints %d\n", prints);
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end
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end
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endmodule
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module clock_init_race(input clk, input reset_l);
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logic m_2_clock;
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logic m_3_clock;
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logic m_2_reset = reset_l;
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logic m_3_reset = reset_l;
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assign m_2_clock = clk;
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assign m_3_clock = clk;
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int m_3_counter;
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initial begin
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$write("*-* START TEST *-*\n");
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end
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always @(posedge clk) begin
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if (m_3_counter == 25) begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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end
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bit m_2_ticked;
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always @(posedge m_2_clock) if (!m_2_reset) begin
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m_2_ticked = 1'b1;
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end
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always @(negedge m_2_clock) m_2_ticked = 1'b0;
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always @(posedge m_3_clock) if (!m_3_reset) begin
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$write("*-* m_3_clocked *-*\n");
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// loop empty - unused loop warning
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while (m_2_ticked);
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m_3_counter += 1;
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end
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endmodule
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