14 lines
388 B
Verilog
14 lines
388 B
Verilog
// -*- Verilog -*-
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2025 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
// lib.map file:
|
|
include ./t_config_libmap/lib.map;
|
|
|
|
library rtllib1 somepath -incdir somedir;
|
|
library rtllib2 somewild*;
|
|
library rtllib3 someexplicit;
|