79 lines
1.8 KiB
Systemverilog
79 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Matthew Ballance
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// SPDX-License-Identifier: CC0-1.0
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// Test array bins - separate bin per value, including InsideRange and AstRange
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module t;
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bit [7:0] data;
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covergroup cg;
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coverpoint data {
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// Array bins: creates 3 separate bins
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bins values[] = {1, 5, 9};
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// Non-array bin: creates 1 bin covering all values
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bins grouped = {2, 6, 10};
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}
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endgroup
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// cg2: exercises InsideRange in array bins (e.g., bins r[] = {[0:3]})
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covergroup cg2;
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cp: coverpoint data {
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bins range_arr[] = {[0:3]}; // InsideRange -> 4 separate bins
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}
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endgroup
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// cg3: exercises AstRange in array bins (e.g., bins r[N] = {[lo:hi]})
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covergroup cg3;
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cp: coverpoint data {
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bins range_sized[4] = {[4:7]}; // AstRange with explicit count
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}
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endgroup
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initial begin
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cg cg_inst;
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cg2 cg2_inst;
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cg3 cg3_inst;
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cg_inst = new();
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cg2_inst = new();
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cg3_inst = new();
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// Hit first array bin value (1)
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data = 1;
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cg_inst.sample();
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// Hit second array bin value (5)
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data = 5;
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cg_inst.sample();
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// Hit the grouped bin (covers all of 2, 6, 10)
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data = 6;
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cg_inst.sample();
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// Hit third array bin value (9)
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data = 9;
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cg_inst.sample();
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// Verify hitting other values in grouped bin doesn't increase coverage
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data = 2;
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cg_inst.sample();
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// Hit range_arr bins (InsideRange [0:3])
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data = 0; cg2_inst.sample();
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data = 1; cg2_inst.sample();
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data = 2; cg2_inst.sample();
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// Hit range_sized bins (AstRange [4:7])
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data = 4; cg3_inst.sample();
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data = 5; cg3_inst.sample();
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data = 6; cg3_inst.sample();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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