53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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int a1[$] = '{12, 13};
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int a2[$] = {14, 15};
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int a3[$] = '{16};
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int a4[$] = {17};
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int src[3], dest1[], dest2[];
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initial begin
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`checkd(a1.size, 2);
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`checkd(a1[0], 12);
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`checkd(a1[1], 13);
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`checkd(a2.size, 2);
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`checkd(a2[0], 14);
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`checkd(a2[1], 15);
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`checkd(a3.size, 1);
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`checkd(a3[0], 16);
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`checkd(a4.size, 1);
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`checkd(a4[0], 17);
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src = '{2, 3, 4};
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dest1 = new[2] (src);
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`checkd(dest1.size, 2); // {2, 3}
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`checkd(dest1[0], 2);
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`checkd(dest1[1], 3);
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dest2 = new[4] (src);
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`checkd(dest2.size, 4); // {2, 3, 4, 0}.
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`checkd(dest2[0], 2);
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`checkd(dest2[1], 3);
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`checkd(dest2[2], 4);
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`checkd(dest2[3], 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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