75 lines
1.3 KiB
Systemverilog
75 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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parameter PAR = 3;
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defparam PAR = 5;
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wire [31:0] o2a, o2b, o3a, o3b;
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m1 #(0) m1a (
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.o2(o2a),
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.o3(o3a)
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);
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m1 #(1) m1b (
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.o2(o2b),
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.o3(o3b)
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);
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generate
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for (genvar i = 0; i < 8; i = i + 1) begin : blk
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m3 u_m3 ();
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defparam blk[i].u_m3.PAR3 = i;
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end
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endgenerate
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always @(posedge clk) begin
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if (PAR != 5) $stop;
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if (o2a != 8) $stop;
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if (o2b != 4) $stop;
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if (o3a != 80) $stop;
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if (o3b != 40) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module m1 (
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output wire [31:0] o2,
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output wire [31:0] o3
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);
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parameter W = 0;
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generate
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if (W == 0) begin
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m2 m2 (.*);
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defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80;
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end
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else begin
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m2 m2 (.*);
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defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40;
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end
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endgenerate
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endmodule
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module m2 (
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output wire [31:0] o2,
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output wire [31:0] o3
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);
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parameter PAR2 = 20;
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assign o2 = PAR2;
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m3 m3 (.*);
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endmodule
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module m3 (
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output wire [31:0] o3
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);
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parameter PAR3 = 40;
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assign o3 = PAR3;
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endmodule
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