57 lines
1.2 KiB
Systemverilog
57 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int m_field = get_ok();
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function int get_ok();
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return 1;
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endfunction
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function void nonstatic();
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endfunction
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function Cls nonstatic_retcls();
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return null;
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endfunction
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static function void isst();
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endfunction
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endclass
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class Bar;
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function void bar();
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Cls::nonstatic(); // <--- bad static ref
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Cls::nonstatic_retcls(); // <--- bad static ref
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Cls::isst();
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endfunction
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endclass
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class Extends extends Cls;
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function void ok();
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nonstatic();
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isst();
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endfunction
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static function void extstatic();
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nonstatic(); // <--- bad static ref
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isst();
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endfunction
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function new();
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Cls c = super.nonstatic_retcls();
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endfunction
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endclass
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module t;
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function void nonclassfunc();
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Cls::nonstatic(); // <--- bad static ref
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Cls::isst();
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endfunction
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initial begin
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Bar obj = new();
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obj.bar();
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Cls::nonstatic(); // <--- bad static ref
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Cls::isst();
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Extends::isst();
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$stop;
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end
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endmodule
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