Files
verilator/docs
Geza Lore ce77bac99a Break some combinational cycles in DFG (#6168)
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00
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Verilator Documentation
=======================

This folder contains sources for Verilator documentation.

For formatted documentation see:

- `Verilator README <https://github.com/verilator/verilator>`_

- `Verilator installation and package directory structure
  <https://verilator.org/install>`_

- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_

- `Subscribe to Verilator announcements
  <https://github.com/verilator/verilator-announce>`_

- `Verilator forum <https://verilator.org/forum>`_

- `Verilator issues <https://verilator.org/issues>`_