60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test std::randomize() called from a static function referencing static
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// class members in the 'with' clause.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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typedef enum bit [3:0] {
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INSTR_ADD = 0,
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INSTR_SUB = 1,
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INSTR_MUL = 2,
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INSTR_AND = 4
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} instr_name_t;
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class instr_base;
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static instr_name_t allowed_instrs[$];
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static function void init();
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allowed_instrs.push_back(INSTR_ADD);
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allowed_instrs.push_back(INSTR_SUB);
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allowed_instrs.push_back(INSTR_MUL);
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allowed_instrs.push_back(INSTR_AND);
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endfunction
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static function instr_name_t get_rand_instr();
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instr_name_t name;
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int ok;
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ok = std::randomize(name) with {name inside {allowed_instrs};};
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`checkd(ok, 1);
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return name;
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endfunction
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endclass
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initial begin
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instr_name_t result;
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instr_base::init();
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repeat (20) begin
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result = instr_base::get_rand_instr();
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`checkd(
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result == INSTR_ADD || result == INSTR_SUB || result == INSTR_MUL || result == INSTR_AND,
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1);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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