63 lines
1.4 KiB
Systemverilog
63 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: FSM coverage negative extraction test
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk
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);
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typedef enum logic [2:0] {
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S0 = 3'd0,
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S1 = 3'd1,
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S2 = 3'd2
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} state_t;
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int cyc;
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logic side;
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logic [2:0] dyn_case;
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state_t state /*verilator fsm_reset_arc*/;
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initial begin
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cyc = 0;
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side = 1'b0;
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dyn_case = 3'd7;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) side <= 1'b1;
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dyn_case <= {2'b11, side};
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// The grouped S0/dyn_case arm keeps the supported S0 baseline while the
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// non-constant case item is skipped. The S1 and default arms are
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// deliberately unsupported extractor shapes: one has two meaningful
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// statements, the other writes a different lhs first. Coverage should ignore
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// those arcs rather than guessing.
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always_ff @(posedge clk) begin
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if (cyc == 0) begin
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state <= S0;
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end
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else begin
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case (state)
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S0, state_t'(dyn_case): state <= S1;
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S1: begin
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side <= ~side;
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state <= S2;
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end
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default: begin
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side <= 1'b0;
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state <= S0;
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end
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endcase
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end
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end
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endmodule
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