120 lines
4.0 KiB
Systemverilog
120 lines
4.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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// Derive signals from non-adjacent CRC bits
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wire a = crc[0];
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wire b = crc[4];
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wire c = crc[8];
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wire d = crc[12];
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int count_fail1 = 0;
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int count_fail2 = 0;
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int count_fail3 = 0;
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int count_fail4 = 0;
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int count_fail5 = 0;
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int count_fail6 = 0;
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int count_fail7 = 0;
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int count_fail8 = 0;
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int count_fail9 = 0;
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int count_fail10 = 0;
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int count_fail11 = 0;
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// Test 1: a[*3] |-> b
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assert property (@(posedge clk) a [* 3] |-> b)
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else count_fail1 <= count_fail1 + 1;
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// Test 2: a[*1] |-> c
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assert property (@(posedge clk) a [* 1] |-> c)
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else count_fail2 <= count_fail2 + 1;
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// Test 3: a[*2] |=> d
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assert property (@(posedge clk) a [* 2] |=> d)
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else count_fail3 <= count_fail3 + 1;
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// Test 4: b[*2] standalone
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assert property (@(posedge clk) b [* 2])
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else count_fail4 <= count_fail4 + 1;
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// Test 5: a[*10000] large count
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assert property (@(posedge clk) a [* 100] |-> b)
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else count_fail5 <= count_fail5 + 1;
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// Test 6: a[*1:3] ##1 b -- bounded range in SExpr
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assert property (@(posedge clk) a [* 1:3] ##1 b)
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else count_fail6 <= count_fail6 + 1;
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// Test 7: a[+] ##1 b -- one-or-more in SExpr
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assert property (@(posedge clk) a [+] ##1 b)
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else count_fail7 <= count_fail7 + 1;
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// Test 8: a[+] |-> b -- standalone [+]
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assert property (@(posedge clk) a [+] |-> b)
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else count_fail8 <= count_fail8 + 1;
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// Test 9: a[*] |-> b -- standalone [*]
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assert property (@(posedge clk) a [*] |-> b)
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else count_fail9 <= count_fail9 + 1;
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// Test 10: a[*1] ##1 b -- trivial [*1] in SExpr (restored to plain SExpr)
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assert property (@(posedge clk) a [* 1] ##1 b)
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else count_fail10 <= count_fail10 + 1;
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// Test 11: a[*] ##1 b -- zero-or-more in SExpr (minN==0 path)
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assert property (@(posedge clk) a [*] ##1 b)
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else count_fail11 <= count_fail11 + 1;
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// Counter FSM with M>0: range > kChainLimit (256) forces counter vertex
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// creation; min>0 exercises the Gte/active gating path in resolveLinks and
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// emitNbaLogic. Cover-only so count_fail values above are undisturbed.
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cover property (@(posedge clk) ##[10:300] b);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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`checkd(count_fail1, 5); // Questa: 5
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`checkd(count_fail2, 25); // Questa: 25
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`checkd(count_fail3, 9); // Questa: 9
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`checkd(count_fail4, 49); // Questa: 49
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`checkd(count_fail5, 0); // Questa: 0
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// NFA merge-node range [*M:N] over-counts rejects (Questa: 51); match
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// detection is correct, only reject counting is imprecise
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`checkd(count_fail6, 59);
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`checkd(count_fail7, 51); // Questa: 51
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`checkd(count_fail8, 20); // Questa: 20
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// IEEE 1800-2023 16.9.2 permits empty match of [*0]; NFA reports
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// rejects on each tick while Questa suppresses (Questa: 20)
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`checkd(count_fail9, 49);
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`checkd(count_fail10, 59); // Questa: 59
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// a[*] ##1 b: NFA treats unbounded [*] as liveness (no reject);
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// Questa treats as definite antecedent (Questa: 29)
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`checkd(count_fail11, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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