20 lines
600 B
Systemverilog
20 lines
600 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a;
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logic b;
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// IEEE-legal but engine has no sim-end liveness.
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assert property (@(posedge clk) always [2:$] a);
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// Nested sequence/property operators inside bounded always.
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assert property (@(posedge clk) always [0:3] (a |-> b));
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assert property (@(posedge clk) always [0:3] (a |=> b));
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assert property (@(posedge clk) always [0:3] (a ##1 b));
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endmodule
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