90 lines
2.5 KiB
Systemverilog
90 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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initial begin
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int tofind;
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int aliases[$];
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int found[$];
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int i;
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byte byteq[$] = {2, -1, 127};
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byte b[];
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logic [7:0] m[2][2];
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logic bit_arr[1024];
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aliases = '{1, 4, 6, 8};
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tofind = 6;
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found = aliases.find with (item == 1);
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`checkh(found.size, 1);
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found = aliases.find(j) with (j == tofind);
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`checkh(found.size, 1);
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// And as function
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aliases.find(i) with (i == tofind);
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// No parenthesis
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tofind = 0;
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found = aliases.find with (item == tofind);
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`checkh(found.size, 0);
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aliases.find with (item == tofind);
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// bug3387
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i = aliases.sum();
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`checkh(i, 'h13);
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i = byteq.sum() with (int'(item));
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`checkh(i, 128);
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// Unique (array method)
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tofind = 4;
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found = aliases.find with (tofind); // "true" match
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`checkh(found.size, 4);
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found = aliases.find() with (item == tofind);
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`checkh(found.size, 1);
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found = aliases.find(i) with (i == tofind);
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`checkh(found.size, 1);
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i = aliases.or(v) with (v);
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`checkh(i, 'hf);
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i = aliases.and(v) with (v);
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`checkh(i, 0);
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i = aliases.xor(v) with (v);
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`checkh(i, 'hb);
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// Based roughly on IEEE 1800-2023 7.12.3
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// verilator lint_off WIDTHEXPAND
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b = {1, 2, 3, 4};
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i = b.sum; // = 10 <= 1 + 2 + 3 + 4
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`checkd(i, 10);
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i = b.product; // = 24 <= 1 * 2 * 3 * 4
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`checkd(i, 24);
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i = b.xor with (item + 4); // = 12 <= 5 ^ 6 ^ 7 ^ 8
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`checkd(i, 12);
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m = '{'{5, 10}, '{15, 20}};
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i = m.sum with (item.sum with (item)); // = 50 <= 5+10+15+20
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`checkd(i, 50);
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// Width of the reduction method's result is the dtype of the with's expression
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// verilator lint_on WIDTHEXPAND
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for (i = 0; i < 1024; ++i) bit_arr[i] = 1'b1;
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i = bit_arr.sum with (int'(item)); // forces result to be 32-bit
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`checkd(i, 1024);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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