28 lines
561 B
Systemverilog
28 lines
561 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc;
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logic [95:0] wide1;
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logic [15:0] wide2[16]; // 256 bits
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logic deep1[24];
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always @(posedge clk) begin
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wide1[31:0] = cyc;
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wide2[2] = cyc[15:0];
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deep1[3] = cyc[0];
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cyc <= cyc + 1;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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