62 lines
955 B
Systemverilog
62 lines
955 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function int f1;
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fork begin
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#1 $stop;
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end join_none
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f1 = 0;
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endfunction
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function int f2;
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fork begin
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int x;
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x = #5 0; $stop;
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end join_none
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f2 = 0;
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endfunction
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event e;
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function int f3;
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fork begin
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int x;
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@e $stop;
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x = 0;
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end join_none
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f3 = 0;
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endfunction
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function int f4;
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fork begin
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int x;
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x = @e 0; $stop;
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end join_none
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f4 = 0;
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endfunction
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int i;
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function int f5;
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fork begin
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int x;
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wait(i == 0) $stop;
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x = 0;
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end join_none
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f5 = 0;
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endfunction
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initial begin
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fork begin
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i = f1();
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$write("*-* All Finished *-*\n");
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$finish;
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end join_none
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end
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endmodule
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