51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class B;
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rand int insideB;
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constraint i {
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insideB inside {[0:10]};
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};
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endclass
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class A;
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rand logic[31:0] rdata;
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rand int delay;
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int i = 97;
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rand B b;
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function new();
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b = new;
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endfunction
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constraint delay_bounds {
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delay inside {[0:2]};
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}
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endclass
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module t;
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A a;
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int i;
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int delay;
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logic[31:0] rdata;
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int b;
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initial begin
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a = new;
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i = 7;
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repeat (120) begin
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a.b.insideB = 3;
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a.delay = 1;
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a.rdata = 3;
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if (a.randomize() with {if (a.delay == 1) a.rdata == i;} == 0) $stop;
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if (a.b.randomize() with {a.b.insideB < 3;} == 0) $stop;
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if (a.delay == 1 && a.rdata != 97) $stop;
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if (a.b.insideB >= 3) $stop;
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if (a.randomize() with {if (a.delay == 1) a.rdata == local::i;} == 0) $stop;
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if (a.delay == 1 && a.rdata != 7) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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