35 lines
715 B
Systemverilog
35 lines
715 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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virtual class uvm_sequence #(
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type REQ = int
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);
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REQ m_req;
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endclass
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endpackage
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package SubPkg;
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import Pkg::*;
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class s_trgt_txn;
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int m_txn_val;
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endclass
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class p_mem_seq extends uvm_sequence #(s_trgt_txn);
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rand bit m_wr_flag;
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virtual task body();
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if (0 !== (m_req.randomize() with {local::m_wr_flag;})) begin
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end
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endtask
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endclass
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endpackage
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module t;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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