25 lines
660 B
Systemverilog
25 lines
660 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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sub u_sub ();
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endmodule
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module sub #(
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parameter INDEX = 4096
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);
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parameter STRG = $sformatf("stringed[%0d]", INDEX);
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initial begin
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`checks(STRG, "stringed[4096]");
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$finish;
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end
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endmodule
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