65 lines
1.4 KiB
Systemverilog
65 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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package pkg;
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function int pkg_func();
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return 1;
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endfunction
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endpackage
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module sub #(
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parameter int X = 1
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) ();
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localparam int Y = X;
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localparam int Z = X;
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function int sub_func();
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return 1;
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endfunction
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endmodule
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module t;
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localparam int MY_X = 2;
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sub #(.X(MY_X)) u_sub ();
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localparam int SUB_Y = u_sub.Y; // <--- BAD: IEEE 1800-2023 6.20.2 no hierarchical
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localparam int SUB_FUNC = u_sub.sub_func(); // <--- BAD: IEEE 1800-2023 6.20.2 no hierarchical
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localparam int OK_FUNC = local_func(); // ok
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localparam int OK_PKG_FUNC = pkg::pkg_func(); // ok
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sub #(.X(block.block_func())) u_sub2 (); // <--- BAD
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begin : block
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function int block_func();
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return 2;
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endfunction
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end
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function int local_func();
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return 2;
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endfunction
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initial begin
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`checkd(SUB_Y, 1);
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`checkd(u_sub.X, 2);
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`checkd(u_sub.Y, 1);
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`checkd(u_sub.Z, 2);
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$finish;
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end
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endmodule
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