23 lines
550 B
Systemverilog
23 lines
550 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam int C[4] = '{5, 6, 7, 8};
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a #(.P(C)) i_a ();
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endmodule
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module a
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#( parameter int P[4] = '{1, 2, 3, 4} );
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initial begin
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if (P[0] != 5) $stop;
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if (P[1] != 6) $stop;
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if (P[2] != 7) $stop;
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if (P[3] != 8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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