36 lines
568 B
Systemverilog
36 lines
568 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface mem_if (
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input wire clk
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);
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logic reset;
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clocking cb @(posedge clk);
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output reset;
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endclocking
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modport mp(input clk, clocking reset, clocking cx);
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endinterface
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module sub (
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mem_if.mp x
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);
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initial begin
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x.cb.reset <= 1;
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end
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endmodule
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module t ();
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logic clk = 0;
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mem_if m_if (clk);
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sub i_sub (m_if);
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endmodule
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