52 lines
1.2 KiB
Systemverilog
52 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface axi_if;
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logic clk;
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wire rlast;
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wire rvalid;
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clocking cb @(posedge clk);
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inout rlast, rvalid;
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endclocking
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modport md1(clocking cb, inout clk, rlast, rvalid);
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modport md2(clocking cb);
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endinterface
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module sub (
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axi_if.md1 axi1,
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axi_if.md2 axi2
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);
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initial begin
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axi1.clk = 1'b0;
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#1 axi1.clk = 1'b1;
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#1 axi1.clk = 1'b0;
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#1 axi1.clk = 1'b1;
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end
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initial begin
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@(negedge axi1.rvalid);
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$display("[%0t] rvalid==%b", $time, axi1.rvalid);
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$display("[%0t] rlast is 1: ", $time, axi1.rlast === 1);
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if (axi1.rlast === 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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$display("[%0t] rvalid <= 1", $time);
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axi1.cb.rvalid <= 1'b1;
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@(posedge axi1.rvalid);
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$display("[%0t] rvalid <= 0", $time);
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axi1.cb.rvalid <= 1'b0;
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@(negedge axi1.clk);
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$display("[%0t] rlast <= 1", $time);
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axi2.cb.rlast <= 1'b1;
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end
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endmodule
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module t;
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axi_if axi_vi ();
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sub i_sub (.axi1(axi_vi), .axi2(axi_vi));
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endmodule
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