40 lines
627 B
Systemverilog
40 lines
627 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module sub #(parameter P);
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endmodule
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package pkg;
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parameter A = 3;
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endpackage
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class B;
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int x;
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endclass
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module Gm (interface a);
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B b;
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sub#(.P(pkg::A + $bits(b.x))) s();
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initial begin
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a.v = s.P;
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end
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endmodule
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interface inf;
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int v;
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endinterface
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module t;
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inf i();
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Gm g(.a(i));
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initial begin
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#1;
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if (i.v != 35) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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