38 lines
943 B
Systemverilog
38 lines
943 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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int callCount = 0;
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int value = 6;
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function int get();
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callCount += 1;
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return value;
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endfunction
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endclass
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module t;
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Foo foo;
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Foo array[100];
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Foo res[$];
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initial begin
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foo = new;
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for (int i = 0; i < 100; ++i) begin
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array[i] = new;
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end
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if (!(foo.get() inside {3,4,5,6,7,8,9})) $stop;
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if (foo.callCount != 1) $stop;
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if (!(foo.get() inside {[3:9]})) $stop;
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if (foo.callCount != 2) $stop;
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res = array.find(x) with (x.get() inside {5,7,8,9});
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if (res.size() != 0) $stop;
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for (int i = 0; i < 100; ++i) begin
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if (array[i].callCount != 1) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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