28 lines
502 B
Systemverilog
28 lines
502 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module liblib_a;
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liblib_b b ();
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endmodule
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module liblib_b;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module liblib_c;
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// Unused
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initial $stop;
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liblib_d d ();
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endmodule
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module liblib_d;
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// Unused
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initial $stop;
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endmodule
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