18 lines
346 B
Systemverilog
18 lines
346 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int x;
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function bit foo;
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x += 1;
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return bit'(x % 2);
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endfunction
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always @(posedge foo());
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endmodule
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