39 lines
1.2 KiB
Systemverilog
39 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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package uvm_pkg;
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class uvm_queue #(type T=int);
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endclass
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class m_uvm_waiter;
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endclass
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class uvm_config_db#(type T=int);
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static local uvm_queue#(m_uvm_waiter) m_waiters[string];
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static function void set(int a, string b, string c, int d);
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endfunction
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endclass
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endpackage
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package sfr_agent_pkg;
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class sfr_monitor_abstract;
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endclass
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endpackage: sfr_agent_pkg
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module sfr_monitor_bfm #(ADDR_WIDTH = 8,
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DATA_WIDTH = 8)
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(
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input [ADDR_WIDTH-1:0] address);
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import uvm_pkg::*;
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import sfr_agent_pkg::*; int SFR_MONITOR;
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initial begin
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uvm_config_db #(sfr_monitor_abstract)::set(null, "uvm_test_top", "SFR_MONITOR", SFR_MONITOR);
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end
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endmodule: sfr_monitor_bfm
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module hdl_top;
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 32;
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sfr_monitor_bfm #(.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)) SFR_MONITOR(
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.address(42));
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endmodule
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