76 lines
1.4 KiB
Systemverilog
76 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface Iface;
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bit clk;
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int x;
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clocking cb @(posedge clk);
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default input #0 output #0;
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inout x;
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endclocking
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endinterface
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class Foo;
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virtual Iface iface;
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function new(virtual Iface tmp);
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iface = tmp;
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endfunction
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task update(virtual Iface tmp);
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iface = tmp;
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endtask
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endclass
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class Bar;
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Foo foo;
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function new(Foo tmp);
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foo = tmp;
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endfunction
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task update(Foo tmp);
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foo = tmp;
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endtask
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task assignment();
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foo.iface.cb.x <= 8;
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endtask
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endclass
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module t;
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Iface iface();
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Iface iface2();
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task clockSome();
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#2;
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iface.clk = ~iface.clk;
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iface2.clk = ~iface2.clk;
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#2;
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iface.clk = ~iface.clk;
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iface2.clk = ~iface2.clk;
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endtask
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initial begin
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Foo foo = new(iface);
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Foo foo2 = new(iface2);
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Bar bar = new(foo);
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clockSome();
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if (iface.x != 0) $stop;
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if (iface2.x != 0) $stop;
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bar.assignment();
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clockSome();
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if (iface.x != 8) $stop;
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if (iface2.x != 0) $stop;
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foo.update(iface2);
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clockSome();
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if (iface.x != 8) $stop;
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if (iface2.x != 0) $stop;
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bar.update(foo2);
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clockSome();
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if (iface.x != 8) $stop;
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if (iface2.x != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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