55 lines
1.4 KiB
Systemverilog
55 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Geza Lore
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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localparam int N = 4096;
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integer cyc = 0;
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reg [63:0] crc = 64'h5aef0c8d_d70a4497;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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reg a[N-1:0];
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reg b[N-1:0];
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// This yields pathological complexity for the current conditional merging
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// algorithm. Note in practice, other parts of the compiler blow up on this
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// code far earlier than the conditional merging, but here we go anyway.
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generate
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genvar i;
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for (i = 0; i < N; i = i + 1) begin
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always @(posedge clk) a[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64];
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end
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for (i = 0; i < N; i = i + 1) begin
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always @(posedge clk) b[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64];
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end
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endgenerate
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always @(posedge clk) begin
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if (cyc >= 2) begin
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for (int i = 0; i < N; i = i + 1) begin
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if (a[i] !== b[i]) begin
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$write("%%Error: %s:%0d: cyc=%0d i=%0d a[i]='h%x b[i]='h%x\n", `__FILE__, `__LINE__, cyc,
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i, a[i], b[i]);
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$stop;
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end
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end
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end
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end
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endmodule
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