100 lines
2.3 KiB
Systemverilog
100 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Tests look for magic string "Dead" not to exist; V3Dead should remove these
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class BaseClass_Dead;
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endclass
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class EmptyClass_Dead extends BaseClass_Dead;
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endclass
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package Pack_Dead;
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typedef bit typedef_Dead;
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endpackage
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module Mod_Dead;
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typedef class ModClass_Co_Dead;
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class ModClass_Dead;
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int m_b_Dead;
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ModClass_Co_Dead m_co_dead;
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task method_Dead;
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endtask
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static task method_static_Dead;
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endtask
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endclass
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class ModClass_Co_Dead;
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ModClass_Dead m_dead; // Check that ModClass_Dead<->ModClass_Co_Dead link gets Deadified
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endclass
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endmodule
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module Mod_Empty_Dead;
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endmodule
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module Mod_Parent_Empty_Dead;
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Mod_Empty_Dead sub ();
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endmodule
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interface If_Dead;
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function void if_func_Dead;
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endfunction
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modport modport_Dead(import if_func_Dead);
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endinterface
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package Pkg_public_kpt;
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parameter int public_int_Keep /*verilator public_flat_rd*/ = 5;
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endpackage
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package Pkg_Keep;
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import "DPI-C" function void dpii_Keep();
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export "DPI-C" function dpix_Keep;
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function void dpix_Keep;
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endfunction
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endpackage
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module t ( /*AUTOARG*/);
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typedef struct {int struct_member_Dead;} struct_Dead_t;
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struct_Dead_t var_struct_Dead;
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typedef int typedef_Dead1_t;
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typedef typedef_Dead1_t typedef_Dead2_t;
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function void func_Dead;
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endfunction
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generate
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if (0) begin
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Mod_Dead cell_nogen_Dead ();
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If_Dead if_nogen_Dead ();
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end
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endgenerate
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Mod_Empty_Dead cell_empty_Dead ();
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Mod_Parent_Empty_Dead cell_parent_empty_Dead ();
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typedef_Dead1_t assigned_to_Dead1;
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typedef_Dead2_t assigned_to_Dead2;
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typedef_Dead2_t assigned_to_Dead3;
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typedef_Dead2_t assigned_to_Dead4;
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typedef_Dead2_t assigned_to_Dead5;
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typedef_Dead2_t assigned_to_Dead6;
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always_comb assigned_to_Dead6 = assigned_to_Dead5;
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always_comb assigned_to_Dead5 = assigned_to_Dead4;
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always_comb assigned_to_Dead4 = assigned_to_Dead3;
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always_comb assigned_to_Dead3 = assigned_to_Dead2;
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always_comb assigned_to_Dead2 = assigned_to_Dead1;
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initial begin
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assigned_to_Dead1 = 1;
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assigned_to_Dead1 = 2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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