70 lines
1.1 KiB
Systemverilog
70 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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q,
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// Inputs
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clk,
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d
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);
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input clk;
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input [3:0] d;
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output wire [3:0] q;
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logic [3:0] between;
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logic direct_named;
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logic computed_named;
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logic anonymous_expr;
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localparam logic [1:0] S_IDLE = 2'b00;
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localparam logic [1:0] S_FETCH = 2'b01;
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localparam logic [1:0] S_EXEC = S_FETCH + 1;
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assign direct_named = d[1:0] == S_IDLE;
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assign computed_named = d[1:0] == S_EXEC;
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assign anonymous_expr = d[1:0] == (S_FETCH + 1);
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mod1 #(
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.WIDTH(4)
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) cell1 (
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.q(between),
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.clk(clk),
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.d(d[3:0])
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);
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mod2 cell2 (
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.d(between),
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.q(q[3:0]),
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.clk(clk)
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);
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endmodule
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module mod1 #(
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parameter WIDTH = 32
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) (
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input clk,
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input [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q
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);
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localparam IGNORED = 1;
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always @(posedge clk) q <= d;
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endmodule
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module mod2 (
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input clk,
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input [3:0] d,
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output wire [3:0] q
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);
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assign q = d;
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endmodule
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