16 lines
291 B
Systemverilog
16 lines
291 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
// SPDX-FileCopyrightText: 2005 Wilson Snyder
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
|
|
looped looped ();
|
|
|
|
endmodule
|
|
|
|
module looped;
|
|
looped looped ();
|
|
endmodule
|