15 lines
293 B
Systemverilog
15 lines
293 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
// SPDX-FileCopyrightText: 2023 Wilson Snyder
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
interface class Icls;
|
|
int badi;
|
|
task badtask;
|
|
endtask
|
|
endclass
|
|
|
|
module t;
|
|
endmodule
|