67 lines
1.8 KiB
Systemverilog
67 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Cross-hierarchy dotted refs through a multi-dim iface array of a
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// parameterized interface. Exercises IfaceCapture plus the multi-dim
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// dotted-access resolver together.
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interface bus_if #(
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parameter int W = 8
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);
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logic [W-1:0] data;
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endinterface
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// Wrapper holding the multi-dim iface array; parent reads its cells via dots.
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module holder;
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localparam int A = 2;
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localparam int B = 3;
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bus_if #(.W(8)) bus[A-1:0][B-1:0] ();
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genvar gi, gj;
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generate
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for (gi = 0; gi < A; gi++) begin : g_a
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for (gj = 0; gj < B; gj++) begin : g_b
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initial bus[gi][gj].data = 8'(gi * B + gj + 5);
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end
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end
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endgenerate
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endmodule
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module t;
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holder h ();
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initial begin
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#1;
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if (h.bus[0][0].data !== 8'd5) begin
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$write("%%Error: h.bus[0][0].data=%0d expected 5\n", h.bus[0][0].data);
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$stop;
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end
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if (h.bus[0][1].data !== 8'd6) begin
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$write("%%Error: h.bus[0][1].data=%0d expected 6\n", h.bus[0][1].data);
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$stop;
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end
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if (h.bus[0][2].data !== 8'd7) begin
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$write("%%Error: h.bus[0][2].data=%0d expected 7\n", h.bus[0][2].data);
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$stop;
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end
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if (h.bus[1][0].data !== 8'd8) begin
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$write("%%Error: h.bus[1][0].data=%0d expected 8\n", h.bus[1][0].data);
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$stop;
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end
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if (h.bus[1][1].data !== 8'd9) begin
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$write("%%Error: h.bus[1][1].data=%0d expected 9\n", h.bus[1][1].data);
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$stop;
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end
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if (h.bus[1][2].data !== 8'd10) begin
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$write("%%Error: h.bus[1][2].data=%0d expected 10\n", h.bus[1][2].data);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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