63 lines
1.5 KiB
Systemverilog
63 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Three-level hierarchy passing a multi-dim iface array by port at each
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// boundary. Top reads leaf's chk array via dotted cross-hier reference,
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// which also exercises the multi-dim dotted-access resolver.
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interface simple_if;
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logic [7:0] data;
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endinterface
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module leaf (
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simple_if b[1:0][2:0]
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);
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logic [7:0] chk[1:0][2:0];
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 3; gj++) begin : g_b
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always_comb chk[gi][gj] = b[gi][gj].data;
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end
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end
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endgenerate
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endmodule
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module mid (
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simple_if b[1:0][2:0]
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);
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leaf leaf_inst (.b(b));
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endmodule
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module t;
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simple_if bus[1:0][2:0] ();
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mid mid_inst (.b(bus));
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_drive_a
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for (gj = 0; gj < 3; gj++) begin : g_drive_b
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initial bus[gi][gj].data = 8'(gi * 3 + gj + 7);
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 3; j++) begin
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if (mid_inst.leaf_inst.chk[i][j] !== 8'(i * 3 + j + 7)) begin
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$write("%%Error: leaf.chk[%0d][%0d]=%0d expected %0d\n",
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i, j, mid_inst.leaf_inst.chk[i][j], i * 3 + j + 7);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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