20 lines
369 B
Systemverilog
20 lines
369 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class c;
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function bit f();
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return 1'b0;
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endfunction
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endclass
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module t;
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c cinst;
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initial begin
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cinst = new();
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if (cinst.f) begin
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end
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end
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endmodule
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