40 lines
863 B
Systemverilog
40 lines
863 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop // TODO
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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// Example from IEEE 1800-2023 10.6.2
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module t;
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logic a, b, c, d;
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wire e;
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and and1 (e, a, b, c);
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initial begin
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$monitor("%d d=%b,e=%b", $stime, d, e);
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d = a & b & c;
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a = 1;
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b = 0;
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c = 1;
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#10;
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force d = (a | b | c);
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force e = (a | b | c);
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`checkh(d, 1);
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`checkh(e, 1);
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#10;
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release d;
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release e;
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#10;
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`checkh(d, 0);
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`checkh(e, 0);
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$finish;
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end
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endmodule
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