28 lines
485 B
Systemverilog
28 lines
485 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int value;
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task increment(ref int i);
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// verilator no_inline_task
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++i;
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endtask
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initial begin
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value = 3;
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increment(value);
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force value = 0;
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$display("ii %d\n", value);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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