69 lines
2.1 KiB
Plaintext
69 lines
2.1 KiB
Plaintext
// // verilator_coverage annotation
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// DESCRIPTION: Verilator: FSM coverage basic test
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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typedef enum logic [1:0] {
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S_IDLE = 2'd0,
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S_RUN = 2'd1,
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S_DONE = 2'd2,
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S_ERR = 2'd3
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} state_t;
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logic rst;
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logic start;
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integer cyc;
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state_t state /*verilator fsm_reset_arc*/;
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initial begin
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rst = 1'b1;
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start = 1'b0;
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cyc = 0;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) rst <= 1'b0;
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if (cyc == 2) start <= 1'b1;
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if (cyc == 3) start <= 1'b0;
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if (cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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end
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else begin
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%000004 case (state)
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// [FSM coverage]
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%000001 // [fsm_arc t.state::ANY->S_IDLE[reset_include]] [reset arc, excluded from %]
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%000004 // [fsm_arc t.state::S_DONE->S_DONE]
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%000003 // [fsm_arc t.state::S_IDLE->S_IDLE]
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%000001 // [fsm_arc t.state::S_IDLE->S_RUN]
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%000001 // [fsm_arc t.state::S_RUN->S_DONE]
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%000001 // [fsm_state t.state::S_DONE]
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%000000 // [fsm_state t.state::S_ERR] *** UNCOVERED ***
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%000000 // [fsm_state t.state::S_IDLE] *** UNCOVERED ***
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%000001 // [fsm_state t.state::S_RUN]
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S_IDLE:
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if (start) state <= S_RUN;
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else state <= S_IDLE;
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S_RUN: state <= S_DONE;
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S_DONE: state <= S_DONE;
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default: state <= S_ERR;
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endcase
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end
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end
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endmodule
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