117 lines
2.3 KiB
Systemverilog
117 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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typedef logic [31:0] uvm_reg_data_t;
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class uvm_object;
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endclass
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class uvm_reg_field extends uvm_object;
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rand uvm_reg_data_t value;
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int unsigned m_size;
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function uvm_reg_data_t get;
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return value;
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endfunction
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function void set_rand_mode(bit rand_mode);
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value.rand_mode(rand_mode);
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uvm_reg_field_valid.constraint_mode(rand_mode);
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endfunction
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function bit get_rand_mode();
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return bit'(value.rand_mode());
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endfunction
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constraint uvm_reg_field_valid {
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if (64'd64 > {32'd0, m_size}) {
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{32'd0, value} < (64'd1 << m_size);
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}
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}
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function void configure(int unsigned size);
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m_size = size;
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endfunction
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endclass
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class uvm_reg extends uvm_object;
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virtual function void build();
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endfunction
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endclass
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class regA extends uvm_reg;
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rand uvm_reg_field fA1;
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rand uvm_reg_field fA2;
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virtual function void build();
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this.fA1 = new;
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this.fA2 = new;
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this.fA1.configure(16);
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this.fA2.configure(16);
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endfunction
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endclass
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class test extends uvm_object;
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regA rg;
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function new;
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rg = new;
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rg.build();
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endfunction
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task run_test;
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uvm_reg_data_t pre_fA1;
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uvm_reg_data_t pre_fA2;
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int rand_ok;
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// Disable fA1, enable fA2
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rg.fA1.set_rand_mode(0);
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rg.fA2.set_rand_mode(1);
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if (rg.fA1.get_rand_mode() != 0) $stop;
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if (rg.fA2.get_rand_mode() != 1) $stop;
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pre_fA1 = rg.fA1.value;
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rand_ok = rg.randomize();
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if (rand_ok != 0) begin
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// fA1 should be unchanged
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if (rg.fA1.get() !== pre_fA1) begin
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$display("%%Error: fA1 changed: got=%0h exp=%0h", rg.fA1.get(), pre_fA1);
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$stop;
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end
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end
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// Re-enable fA1, disable fA2
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rg.fA1.set_rand_mode(1);
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rg.fA2.set_rand_mode(0);
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pre_fA2 = rg.fA2.value;
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rand_ok = rg.randomize();
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if (rand_ok != 0) begin
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// fA2 should be unchanged
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if (rg.fA2.get() !== pre_fA2) begin
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$display("%%Error: fA2 changed: got=%0h exp=%0h", rg.fA2.get(), pre_fA2);
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$stop;
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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endclass
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module top;
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initial begin
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test t;
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t = new;
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t.run_test();
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end
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endmodule
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